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ACPM-5013 3 x 3 mm power amplifier module lte band13/14 (777-798 mhz) data sheet description the ACPM-5013 is a fully matched 10-pin surface mount module developed for lte band 13 and band 14, operating in the 777-798 mhz bandwidth. the ACPM-5013 meets stringent lte linearity requirements up to 27.5 dbm output power (mpr = 0 db). the 3 x 3 mm form factor package is self contained, incorporating 50 ohm input and output matching networks. the pa also contains internal dc blocking capacitors for rf input and output ports. the ACPM-5013 features 5 th generation of coolpam (coolpam5) circuit technology which supports 3 power modes C bypass, mid and high power modes. the coolpam is stage bypass technology enhancing pae (power added efficiency) at low and medium power range. the active bypass feature is added to coolpam5 to enhance the pae further at low output range and it enables the pa to have exceptionally low quiescent current. it dramatically saves the average power consumption and accordingly extends the talk time of mobiles and prolongs a battery life. a directional coupler is integrated into the module and both coupling and isolation ports are available exter- nally, supporting daisy chain. the integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. the coupler directivity, or the output power variation into the mismatched load, is critical to the trp and sar per- formance of the mobile phones in real field operations as well as compliance tests for the system specifications. the ACPM-5013 has integrated on-chip vref and on- module bias switch as the one of the key features of the coolpam-5, so an external constant voltage source is not required, eliminating the external ldo regulators and switches from circuit boards of mobile devices. it also makes the pa fully digital-controllable by the ven pin that simply turns the pa on and off from the digital control logic input from baseband chipsets. all of the digital control input pins such as the ven, vmode and vbp are fully cmos features thin package (0.9 mm typ) excellent linearity compliant with 3gpp public safety band emission (ns_07) spec 3-mode power control with vbp and vmode bypass / mid power mode / high power mode high efficiency at max output power 10-pin surface mounting package internal 50 ohm matching networks for both rf input and output integrated coupler coupler and isolation ports for daisy chain lead-free, rohs compliant, green applications lte band13 / band 14 handset and data card ordering information part number number of devices container ACPM-5013-tr1 1000 178mm (7) tape/reel ACPM-5013-blk 100 bulk description( cont.) compatible and can operate down to the 1.35 v logic. the current consumption by digital control pins is negligible. the power amplifier is manufactured on an advanced ingap hbt (hetero-junction bipolar transistor) mmic (microwave monolithic integrated circuit) technology offering state-of-the-art reliability, temperature stability and ruggedness.
2 absolute maximum ratings no damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. description min. typ. max. unit rf input power (pin) 0 10.0 dbm dc supply voltage (vcc1, vcc2) 0 3.4 5.0 v enable voltage (ven) 0 2.6 3.3 v mode control voltage (vmode) 0 2.6 3.3 v bypass control (vbp) 0 2.6 3.3 v storage temperature (tstg) -55 25 +125 c recommended operating condition description min. typ. max. unit dc supply voltage (vcc1, vcc2) 3.2 3.4 4.2 v enable voltage (ven) low high 0 1.35 0 2.6 0.5 3.1 v v mode control voltage (vmode) low high 0 1.35 0 2.6 0.5 3.1 v v bypass control voltage (vbp) low high 0 1.35 0 2.6 0.5 3.1 v v operating frequency (fo) 777 798 mhz ambient temperature (ta) -30 25 90 c operating logic table power mode ven vmode vbp pout (lte mpr = 0 db) high power mode high low low ~ 27.5 dbm mid power mode high high low ~ 16 dbm bypass mode high high high ~ 6 dbm shut down mode low low low C
3 electrical characteristics C conditions: vcc = 3.4 v, ven = 2.6 v, ta = 25 c, zin/zout = 50 ohm characteristics condition min. typ. max. unit operating frequency range ? 777 C 798 mhz maximum output power (high power mode) lte, mpr=0db 27.5 dbm gain high power mode, pout = 27.5 dbm 29 32.5 db mid power mode, pout = 16 dbm 19 23.5 db bypass mode, pout = 6 dbm 10 14 db band 13 gain variation gain variation across 777 mhz ~ 787 mhz +/- 0.25 db band 13 rx band noise power (-31 mhz offset from tx carrier, average over +/-4.5 mhz ) wireless carrier specification (1 rb ~ 15 rb) -127 dbm/hz 3gpp specification (20 rb) -123 dbm/hz band 13 ns_07 ps emissions 1 763 ~ 775 mhz, pout < (maximum power C mpr C a-mpr) -59 -57 dbm/6.25 khz rx band gain where g is gain in tx band g + 1 db media band gain where g is gain in tx band, 716 ~ 728 mhz gdb gps and glonass band gain where g is gain in tx band g - 50 db ism band gain where g is gain in tx band, 2400 ~ 2483.5mhz g - 70 db power added efficiency high power mode, pout = 27.5 dbm 33 36 % mid power mode, pout = 16 dbm 13.2 18 % bypass mode, pout = 6 dbm 5.6 10 % total supply current high power mode, pout = 27.5 dbm 400 450 500 ma mid power mode, pout = 16 dbm 50 65 90 ma bypass mode, pout = 6 dbm 7 11 16 ma bypass mode, pout = 3.5 dbm 9 ma quiescent current high power mode 80 105 140 ma mid power mode 10 18 28 ma bypass mode 1 3 5 ma enable current high power mode 4 a mid power mode 4 a bypass mode 4 a mode control current mid power mode 4 a bypass mode 4 a bypass control current bypass 2 a total current in power-down mode ven = 0 v, vmode = 0 v, vbp = 0 v 5 a lte adjacent channel leakage ratio e-utra aclr pout < (maximum power C mpr) -39 -33 dbc utra aclr1 pout < (maximum power C mpr) -42 -36 dbc utra aclr2 pout < (maximum power C mpr) -43 -39 dbc harmonic suppression (2 fo) pout < (maximum power C mpr) -52 -45 dbc harmonic suppression (3 fo and up) pout < (maximum power C mpr) -60 -45 dbc
4 electrical characteristics (continued) characteristics condition min. typ. max. unit input vswr high power mode 2:1 mid power mode 2:1 bypass mode 2:1 stability (spurious output) vswr 5:1, all phase -70 dbc phase discontinuity low power mode mid power mode, at pout = 7 dbm 15 deg mid power mode high power mode, at pout = 16 dbm 10 deg ruggedness pout < 27.5 dbm, pin < 10 dbm, all phase high power mode 10:1 vswr coupling factor rf out to cpl port -20 db daisy chain insertion loss iso port to cpl port, ven = low 686 ~ 2620 mhz 0.25 db * note 1: all signal configurations based on 3gpp ts 36.101 (v.9.3.0) 6.2.4
5 footprint all dimensions are in millimeter x-ray top view pin descriptions pin # name description 1 vcc1 dc supply voltage 2 rfin rf input 3 vbp bypass control 4 vmode mode control 5 ven pa enable 6 cpl coupling port of coupler 7 gnd ground 8 iso isolation port of coupler 9 rfout rf out 10 vcc2 dc supply voltage 0.125 0.10 0.35 0.35 0.60 0.10 1.50 0.25 0.3 pin 1 2.80
6 package dimensions all dimensions are in millimeter marking specification 2 3 4 pin 1 mark 1 5 9 8 7 10 6 3 0.1 3 0.1 0.5 0.9 0.1 pi n 1 mar k ma nuf a ctu ri ng par t numbe r lot numbe r p ma nuf a ctu ri ng info yy ma nuf a ctu ri ng ye ar ww wo r k week aaaaa assemby lot numbe r ; a5013 pyyww aaaaa
7 metallization solder mask opening solder paste stencil aperture pcb design guidelines the recommended pcb land pattern is shown in figures on the left side. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown here. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. con- sidering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. 0.30 0.60 0.35 0.55 0.45 o n 0.5 mm pit c h ? 0.3 mm 0.475 co nn ec t e d t o a inn e r la ye r thr o u g h a via h o l e fo r a be tt e r i so lati o n be tw ee n cpl_i n (iso) and rf o ut 0.65 0.45 0.50 0.60 1.50 1.30 0.525 0.55 0.45 1.10 1.10 0.60 0.35 0.475
8 c1 c2 c3 c4 c6 c5 c7 a 5013 pyyww aaaaa evaluation board schematic evaluation board description 1 v cc 1 2 rf in 3 v b p 4 v mo d e 5 v e n v cc 2 10 rf out 9 g n d 7 cpl 6 v e n v mo d e rf in v cc 1 v cc 2 i so lati o n c1 100 pf c2 100 pf 2.2 f c6 c7 680 pf c4 680 pf c5 2.2 f v b p c3 100 pf iso 8 rf out c o upl e r 50 o h m
9 tape and reel information dimension list annote millimeter a0 3.400.10 b0 3.400.10 k0 1.350.10 d0 1.550.05 d1 1.600.10 p0 4.000.10 p1 8.000.10 annote millimeter p2 2.000.05 p10 40.000.20 e 1.750.10 f 5.500.05 w 12.000.30 t 0.300.05 tape and reel format C 3 mm x 3 mm a 5013 pyyww aaaaa
10 plastic reel format (all dimensions are in millimeters) reel drawing notes: 1. reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. avago technologies part number c. purchase order number d. date code e. quantity of units 2. a certi?cate of compliance (c of c) shall be issued and accompany each shipment of product. 3. reel must not be made with or contain ozone depleting materials. 4. all dimensions in millimeters (mm) 50 m i n . 1 2.4 + 2.0 - 0.0 1 8.4 m a x . 25 m i n wid e ( r ef) s lot fo r c arri e r t ap e i nse r t i on fo r a tt a chment to r eel hub ( 2 p l a ces 1 80 apar t) ba c k view f ro nt view 1 78 s h adi ng i n di c a tes th r u slots + 0.4 - 0.2 2 1 .0 0.8 1 3.0 0.2 1 .5 m i n .
11 handling and storage esd (electrostatic discharge) electrostatic discharge occurs naturally in the environ- ment. with the increase in voltage potential, the outlet of neutralization or discharge will be sought. if the acquired discharge route is through a semiconductor device, destructive damage will result. esd countermeasure methods should be developed and used to control potential esd damage during handling in a factory environment at each manufacturing site. msl (moisture sensitivity level) plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. avago technologies follows jedec standard j-std 020b. each component and package type is classified for moisture sensitivity by soaking a known dry package at moisture classification level and floor life msl level floor life (out of bag) at factory ambient =< 30c/60% rh or as stated 1 unlimited at =< 30c/85% rh 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 mandatory bake before use. after bake, must be reflowed within the time limit specified on the label note : 1. the msl level is marked on the msl label on each shipping bag. various temperatures and relative humidity, and times. after soak, the components are subjected to three con- secutive simulated reflows. the out of bag exposure time maximum limits are deter- mined by the classification test describe below which cor- responds to a msl classification level 6 to 1 according to the jedec standard ipc/jedec j-std-020b and j-std-033. ACPM-5013 is msl3. thus, according to the j-std-033 p.11 the maximum manufacturers exposure time (met) for this part is 168 hours. after this time period, the part would need to be removed from the reel, de-taped and then re-baked. msl classification reflow temperature for the ACPM-5013 is targeted at 260c +0/-5c. figure and table on next page show typical smt profile for maximum temperature of 260 +0/-5c.
12 reflow profile recommendations typical smt reflow profile for maximum temperature = 260 +0/-5c 25 t i me tem p e ra tu r e t p t l t p t l t 25 c to p e a k ra m p -u p ts ts m i n ra m p - d o w n pr ehe a t cri t i c a l zone t l to t p ts m a x typical smt reflow profile for maximum temperature = 260 +0/-5c profile feature sn-pb solder pb-free solder average ramp-up rate (tl to tp) 3c/sec max 3c/sec max preheat C temperature min (tsmin) C temperature max (tsmax) C time (min to max) (ts) 100c 150c 60-120 sec 150c 200c 60-120 sec tsmax to tl C ramp-up rate 3c/sec max time maintained above: C temperature (tl) C time (tl) 183c 60-150 sec 217c 60-150 sec peak temperature (tp) 240 +0/-5c 260 +0/-5c time within 5c of actual peak temperature (tp) 10-30 sec 20-40 sec ramp-down rate 6c/sec max 6c/sec max time 25c to peak temperature 6 min max. 8 min max.
13 storage condition packages described in this document must be stored in sealed moisture barrier, antistatic bags. shelf life in a sealed moisture barrier bag is 12 months at <40c and 90% relative humidity (rh) j-std-033 p.7. out-of-bag time duration after unpacking the device must be soldered to the pcb within 168 hours as listed in the j-std-020b p.11 with factory conditions <30c and 60% rh. baking it is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. baking must be done if at least one of the con- ditions above have not been satisfied. the baking condi- tions are 125c for 12 hours j-std-033 p.8. caution tape and reel materials typically cannot be baked at the temperature described above. if out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (see moisture sensitive warning label on each shipping bag for information of baking). board rework component removal, rework and remount if a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200c. this method will minimize moisture related component damage. if any component temperature exceeds 200c, the board must be baked dry per 4-2 prior to rework and/or component removal. component temperatures shall be measured at the top center of the package body. any smd packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. removal for failure analysis not following the above requirements may cause moisture/ reflow damage that could hinder or completely prevent the determination of the original failure mechanism. baking of populated boards some smd packages and board materials are not able to withstand long duration bakes at 125c. examples of this are some fr-4 materials, which cannot withstand a 24 hr bake at 125c. batteries and electrolytic capacitors are also temperature sensitive. with component and board temperature restrictions in mind, choose a bake tem- perature from table 4-1 in j-std 033; then determine the appropriate bake duration based on the component to be removed. for additional considerations see ipc-7711 andipc-7721. derating due to factory environmental conditions factory floor life exposures for smd packages removed from the dry bags will be a function of the ambient envi- ronmental conditions. a safe, yet conservative, handling approach is to expose the smd packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. this approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30c/60% rh. a solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. jesd22-a120). recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. table on next page lists equivalent derated floor lives for humidities ranging from 20-90% rh for three tempera- ture, 20c, 25c, and 30c. table on next page is applicable to smds molded with novolac, biphenyl or multifunctional epoxy mold compounds. the following assumptions were used in cal- culating this table: 1. activation energy for diffusion = 0.35ev (smallest known value). 2. for 60% rh, use diffusivity = 0.121exp ( -0.35ev/kt) mm2/s (this used smallest known diffusivity @ 30c). 3. for >60% rh, use diffusivity = 1.320exp ( -0.35ev/kt) mm2/s (this used largest known diffusivity @ 30c).
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. av02-2666en - april 13, 2011 recommended equivalent total floor life (days) @ 20c, 25c & 30c, 35c for ics with novolac, biphenyl and multifunctional epoxies (reflow at same temperature at which the component was classified) maximum percent relative humidity maximum percent relative humidity package type and body thickness moisture sensitivity level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% body thickness 3.1 mm including pqfps >84 pin, plccs (square) all mqfps or all bgas 1 mm level 2a 94 124 167 231 44 60 78 103 32 41 53 69 26 33 42 57 16 28 36 47 7 10 14 19 5 7 10 13 4 6 8 10 35c 30c 25c 20c level 3 8 10 13 17 7 9 11 14 6 8 10 13 6 7 9 12 6 7 9 12 4 5 7 10 3 4 6 8 3 4 5 7 35c 30c 25c 20c level 4 3 5 6 8 3 4 5 7 3 4 5 7 2 4 5 7 2 3 5 7 2 3 4 6 2 3 3 5 1 2 3 4 1 2 3 4 35c 30c 25c 20c level 5 2 4 5 7 2 3 5 7 2 3 4 6 2 2 4 5 1 2 3 5 1 2 3 4 1 2 2 3 1 1 2 3 1 1 2 3 35c 30c 25c 20c level 5a 1 2 3 5 1 1 2 4 1 1 2 3 1 1 2 3 1 1 2 3 1 1 2 2 1 1 1 2 1 1 1 2 1 1 1 2 35c 30c 25c 20c body 2.1 mm thickness <3.1 mm including plccs (rectangular) 18-32 pin soics (wide body) soics 20 pins, pqfps 80 pins level 2a 58 86 148 30 39 51 69 22 28 37 49 3 4 6 8 2 3 4 5 1 2 3 4 35c 30c 25c 20c level 3 12 19 25 32 9 12 15 19 7 9 12 15 6 8 10 13 5 7 9 12 2 3 5 7 2 2 3 5 1 2 3 4 35c 30c 25c 20c level 4 5 7 9 11 4 5 7 9 3 4 5 7 3 4 5 6 2 3 4 6 2 3 4 5 1 2 3 4 1 2 2 3 1 1 2 3 35c 30c 25c 20c level 5 3 4 5 6 2 3 4 5 2 3 3 5 2 2 3 4 2 2 3 4 1 2 3 4 1 1 2 3 1 1 1 3 1 1 1 2 35c 30c 25c 20c level 5a 1 2 2 3 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 0.5 0.5 1 2 0.5 0.5 1 1 35c 30c 25c 20c body thickness <2.1 mm including soics <18 pin all tqfps, tsops or all bgas <1 mm body thickness level 2a 17 28 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 3 8 11 14 20 5 7 10 13 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 4 7 9 12 17 4 5 7 9 3 4 5 7 2 3 4 6 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 5 7 13 18 26 3 5 6 8 2 3 4 6 2 2 3 5 1 2 3 4 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 5a 7 10 13 18 2 3 5 6 1 2 3 4 1 1 2 3 1 1 2 2 1 1 2 2 1 1 1 2 0.5 1 1 2 0.5 0.5 1 1 35c 30c 25c 20c

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